The Microsecond Edge in Quantitative Trading
In the high-stakes environment of electronic trading, the difference between profit and loss is often measured in microseconds. The long-running market “race to zero” has shifted from simple execution speed to the ability to run complex machine learning (ML) inference on live market data without introducing systemic lag across the trading stack.
The latest independent audit from STAC-ML (Markets) Inference confirms a significant leap in this capability, as myrtle.ai has demonstrated a drastic reduction in latency using its VOLLO product. STAC benchmarks are widely used by banks, proprietary trading firms, and infrastructure providers as de facto industry standards when assessing technology that could affect market fairness, resilience, and best-execution obligations.
The benchmark results show that VOLLO achieved latencies as low as 2 microseconds at the 99th percentile. By halving previous records, the technology allows quantitative traders to implement more sophisticated models-which typically require more compute time-while maintaining the deterministic speed necessary for real-time risk analysis, quote generation, and compliance with time-critical trading controls.
Hardware Synergy and Adaptive Architecture
Achieving microsecond-level inference requires moving away from general-purpose CPU or GPU architectures, which often suffer from “jitter” or unpredictable latency spikes when contention or background processes intervene. Instead, the focus in ultra-low-latency trading has shifted toward Field Programmable Gate Arrays (FPGAs) and Adaptive SoCs, which allow for hardware-level optimization of the ML model’s data path and more predictable performance under load.
The system utilized in the STAC-ML audit relies on a tightly integrated stack designed to eliminate bottlenecks between the network interface and the inference engine. In practice, that means tuning each layer-from network ingress to application logic-to avoid serialization delays that could compound into missed market opportunities or control breaches.
| Component | Technical Specification |
|---|---|
| Accelerator Card | Silicom FBAP4@VP18-2L0S PCIe card |
| Adaptive SoC | AMD Versal™ Premium series VP1802 |
| Host Server | Supermicro AS-2015CS-TNR |
| Interconnect | PCIe Gen5x8 |
| Logic Capacity | Over 3.3 million programmable LUTs |
“Since VOLLO first exploited the full potential of FPGAs in this STAC benchmark in 2023, we have worked with our customers to further reduce latencies, expand the variety and size of models that VOLLO can run, and grow the range of platforms it can run on,” said Peter Baldwin, CEO of myrtle.ai. “We’re excited to work with AMD, Silicom and Supermicro on this benchmark, to demonstrate how our combined technologies can enable ultra-low latency AI inference in quant trading.”
Deterministic Performance and Market Infrastructure Risk
For financial institutions, the 99th percentile latency is a critical metric because it represents the practical “worst-case” scenario that risk managers and regulators increasingly scrutinize. In a volatile market, a spike in latency-even for a fraction of a second-can lead not only to missed trades or failed hedges, but also to breaches of internal risk limits and regulatory expectations around orderly trading.
The deterministic nature of FPGA-based inference helps ensure that model response time remains effectively constant regardless of market volatility. That predictability is central to how firms demonstrate control over automated systems under rules such as the U.S. Securities and Exchange Commission’s Regulation SCI, which focuses on the stability and resilience of key trading and market infrastructure systems.
This infrastructure allows firms to train models in standard ML environments and then compile them directly into hardware, bypassing the need for manual HDL (Hardware Description Language) coding, which has historically been a barrier to deploying AI in high-frequency trading (HFT) environments. Lowering that barrier could broaden the range of institutions able to deploy advanced, tightly governed models at the network edge, rather than reserving such capabilities solely for specialist shops.
“The future of financial markets will be shaped by AI systems that can interpret data and act on it in near real time,” said Girish Malipeddi, director for Data Center FPGA business, AMD. “With AMD Versal™ Premium series adaptive SoCs at the foundation, myrtle.ai’s VOLLO demonstrates how advanced, low-latency inference can help unlock a new generation of intelligent trading infrastructure.”
“Supermicro continues to address a wide range of markets with our AMD systems, which were used for this STAC-ML benchmark,” said Michael McNerney, Senior Vice President Marketing and Network Security, Supermicro. “Our servers address the most challenging workloads in the financial services industry, and together with partners, we are able to deliver top-end performance with very low latencies for machine learning workloads.”
The integration of these components addresses the critical need for high-bandwidth, low-latency data movement. By leveraging PCIe Gen5, the system minimizes the transport time between the server’s memory and the FPGA’s programmable logic, ensuring the processor is fed with market data as quickly as the physical layer allows, and helping firms maintain tight control loops between data ingestion, model inference, and order routing.
“We’re pleased that myrtle.ai selected Silicom’s Artena accelerator card, based on AMD Versal Premium, for these tests. Built around one of the largest FPGAs in a PCIe form factor, Artena is an ideal platform for VOLLO. Together, VOLLO and our low-latency hardware deliver deterministic, microsecond-level inference for demanding trading workloads,” said Anders Poulsen, VP Solutions at Silicom Denmark.
For market operators, supervisors, and institutional risk committees, independently validated benchmarks such as STAC-ML offer a way to compare emerging AI-driven trading infrastructure against both legacy systems and evolving regulatory expectations. Full technical validation and the complete set of results for the system under test (SUT ID MRTL260323) are documented via STAC Research.
